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United States Patent Application 20050021926
Kind Code A1
Liao, Yu-Chung C. ; et al. January 27, 2005
Method and apparatus for efficient loading and storing of vectors
Abstract
A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.
Inventors: Liao, Yu-Chung C.; (Austin, TX) ; Sandon, Peter A.; (Essex Junction, VT) ; Cheng, Howard; (Redmond, WA)
Correspondence Name and Address: NIXON & VANDERHYE, PC 1100 N GLEBE ROAD 8TH FLOOR ARLINGTON VA 22201-4714 US
Assignee Name and Adress: Nintendo Co., Ltd. Kyoto JP
Serial No.: 849804
Series Code: 10
Filed: May 21, 2004
U.S. Current Class: 712/4
U.S. Class at Publication: 712/004
Intern´l Class: G06F 015/00
Claims
1-39. (Cancelled)
40. A method of loading a vector from memory, comprising: providing a vector in memory; and embedding a location identifier in bits comprising a vector load instruction, wherein the location identifier indicates an ending location in the vector where useful data ends.
41. The method of claim 40, further including using the location indicator when executing the vector load instruction to load only the useful data from the vector into a vector register.
42. The method of claim 41, further including setting remaining locations in the vector register beyond the useful data to a constant.
43. The method of claim 42, further including providing a constant in the vector load instruction for use in setting the remaining locations in the vector to the constant.
44. The method of claim 40, further including providing dedicated bits in the vector load instruction which provide the location identifier.
45. The method of claim 44, wherein a dimension of the vector is 2.sup.n, and further including providing n bits in the vector load instruction to provide the location identifier.
46. The method of claim 40, further including using the vector load instruction in a data processor having a paired singles execution unit, wherein two single precision values constitute the vector.
47. A method of storing a vector from a vector register to memory, comprising: providing the vector in a vector register; and embedding a location identifier in bits comprising a vector store instruction, wherein the location identifier indicates a location in the vector register where useful data ends.
48. The method of claim 47, further including using the location identifier when executing the vector store instruction to store only the useful data in the vector register to memory.
49. The method of claim 47, further including providing dedicated bits in the vector store instruction which provide the location identifier.
50. The method of claim 49, wherein a dimension of the vector is 2.sup.n, and further including providing n bits in the vector store instruction to provide the location identifier.
51. The method of claim 47, further including using the vector store instruction in a data processor having a paired singles execution unit, wherein two single precision values constitute the vector.
52. A data processor, comprising a vector processing unit, a vector register file, a load/store unit and an instruction set, wherein the instruction set includes at least one vector load instruction having a bit format in which an ending location of useful data within the vector is embedded.
53. The data processor of claim 52, wherein the vector load instruction further includes bits which provide a constant to be used by the load/store unit to set locations in a vector register file beyond the useful data to the constant.
54. The data processor of claim 52, wherein at least one dedicated bit is provided in the bit format of the instruction to provide the ending location of the useful data within the vector.
55. The data processor of claim 54, wherein the vector has a dimension of 2.sup.n and n dedicated bits are provided in the instruction to provide the ending location of the useful data.
56. The data processor of claim 52, wherein the vector has a dimension of two.
57. The data processor of claim 52, wherein the vector processing unit is a paired singles unit which processes two single-precision floating point values in parallel.
58. A data processor, comprising a vector processing unit, a vector register file, a load/store unit and an instruction set, wherein the instruction set includes at least one vector store instruction having a bit format in which an ending location of useful data within the vector is embedded.
59. The data processor of claim 58, wherein at least one dedicated bit is provided in the bit format of the instruction to provide the ending location of the useful data within the vector.
60. The data processor of claim 59, wherein the vector has a dimension of 2.sup.n and n dedicated bits are provided in the instruction to provide the ending location of the useful data.
61. The data processor of claim 58, wherein the vector has a dimension of two.
62. The data processor of claim 58, wherein the vector processing unit is a paired singles unit which processes two single-precision floating point values in parallel.
63. A vector load instruction for a data processor, comprising a bit format which includes bits designating a source address where a vector is located, at least one bit which indicates an ending location of useful data within the vector, a value field which provides a constant for use in loading destination vector register locations beyond the useful data, and a destination vector register to be loaded.
64. The vector load instruction of claim 63, wherein the dimension of the vector is 2.sup.n, and n bits are provided in the instruction for indicating the ending location of the useful data within the vector.
65. A vector store instruction for a data processor, comprising a bit format which includes bits designating a source register containing a vector, at least one position bit which indicates an ending location of useful data within the vector, and a destination address for the vector.
66. The vector store instruction of claim 65, wherein the dimension of the vector is 2.sup.n, and n bits are provided in the instruction for indicating the ending location of the useful data within the vector.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to U.S. application Ser. No. ______, entitled "METHOD AND APPARATUS FOR OBTAINING A SCALAR VALUE DIRECTLY FROM A VECTOR REGISTER" and U.S. application Ser. No. ______, entitled "METHOD AND APPARATUS FOR SOFTWARE MANAGEMENT OF ON-CHIP CACHE", filed by the same inventors on the same date as the instant application. Both of these related cases are hereby incorporated by reference in their entirety.
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