Déja ils se trompent puisque le nom de code du Xenos c´est "C1"
"A name that has long since been mentioned in relation to the graphics behind Xenon (the development name for XBOX 360) is R500. Although this name has appeared from various sources, the actual development name ATI uses for Xenon´s graphics is "C1", whilst the more "PR friendly" codename that has surfaced is "Xenos". ATI are probably fairly keen not to use the R500 name as this draws parallels with their upcoming series of PC graphics processors starting with R520, however R520 and Xenos are very distinct parts. R520´s aim is obviously designed to meet the needs of the PC space and have Shader Model 3.0 capabilities as this is currently the highest DirectX API specification available on the PC, and as such these new parts still have their lineage derived from the R300 core, with discrete Vertex and Pixel Shaders; Xenos, on the other hand, is a custom design specifically built to address the needs and unique characteristics of the game console. ATI had a clean slate with which to design on and no specified API to target. These factors have led to the Unified Shader design, something which ATI have prototyped and tested prior to its eventual implementation (with the rumoured R400 development?), with capabilities that don´t fall within any corresponding API specification. Whilst ostensibly Xenos has been hailed as a Shader Model 3.0 part, its capabilities don´t fall directly inline with it and exceed it in some areas giving this more than a whiff of WGF2.0 (Windows Graphics Foundation 2.0 - the new name for DirectX Next / DirectX 10) about it.
The Xenos graphics processor is not a single element, but actually consists of two distinct elements: the graphics core (shader core) and the eDRAM module. The shader core is a 90nm chip manufactured by TSMC and is currently slated to run at 500MHz*, whilst the eDRAM module is another 90nm chip, manufactured by NEC and runs at 500MHz* as well. These two chips both exist side by side, together on a single package, ensuring a fast interlink between the two. The main graphics chip, the parent core, could be considered as a "shader core" as this is one of its primary tasks. The eDRAM module is a separate, daughter chip which contains the elements for reading and writing color, z and stencil and performing all of the alpha blending and z and stencil ops, including the FSAA logic. We´ll explore the capabilities and operations of both these chips in greater detail throughout the article.
(*) Note: We understand the clockspeeds for the shader core and daughter die are target clockspeeds at present and there may be some room for small movement either way on both dies dependant on yields. As Microsoft have now announced 500MHz speeds it is more likely that these will be the eventual release speeds.
One element that has been reported on is the number of 150M transistors in relation to the graphics processing elements of Xenon, however according to ATI this is not correct as the shader core itself is comprised from in the order of 232M transistors. It may be that the 150M transistor figure pertains only to the eDRAM module as with 10MB of DRAM, requiring one transistor per bit, 80M transistors will be dedicated to just the memory; when we add the memory control logic, Render Output Controllers (ROP´s) and FSAA logic on top of that it may be conceivable to see an extra 70M transistors of logic in the eDRAM module."
http://www.beyond3d.com/articles/xenos/index.php?p=02#c1
