Champ Valeur
Propriétés du chipset North Bridge
North Bridge AMD Hammer IMC
Révision 00
In-Order Queue Depth 8
Contrôleur mémoire
Type Dual Channel (128 bits)
Mode actif Single Channel (64 bits)
Performances mémoire
CAS Latency (CL) 3T
RAS To CAS Delay (tRCD) 4T
RAS Precharge (tRP) 4T
RAS Active Time (tRAS) 8T
Row Cycle Time (tRC) 12T
Row Refresh Cycle Time (tRFC) 24T
Command Rate (CR) 2T
RAS To RAS Delay (tRRD) 2T
Write Recovery Time (tWR) 3T
Read To Write Delay (tRTW) 4T
Write To Read Delay (tWTR) 2T
Write CAS Latency (tWCL) 1T
Refresh Period (tREF) 200 MHz 7.8 us
DQS Skew Control Désactivé(e)
DRAM Drive Strength Normal
DRAM Data Drive Strength 4 (No Reduction)
Max Async Latency 7 ns
Read Preamble Time 5.5 ns
Idle Cycle Limit 16
Dynamic Idle Cycle Counter Activé
Read/Write Queue Bypass 8
Bypass Max 4
32-byte Granularity Activé
Correction d´erreurs
ECC Géré, Activé
ChipKill ECC Géré, Désactivé(e)
RAID Non géré
DRAM Scrub Rate Désactivé(e)
L1 Data Cache Scrub Rate Désactivé(e)
L2 Cache Scrub Rate Désactivé(e)
Slots mémoire
Slot DRAM nº1 512 Mo (PC3200 DDR SDRAM)
Slot DRAM nº2 1024 Mo (PC3200 DDR SDRAM)
Fabricant du chipset
Nom de l´entreprise Advanced Micro Devices, Inc.
Information sur le
produit http://www.amd.com/us-en/Processors/Develo
pWithAMD/0,,30_2252_873,00.html
Télécharger le
pilote http://www.amd.com/us-en/Processors/Technic
alResources/0,,30_182_871_2336,00.html